supertex inc. md1213 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com features ? 6.0ns rise and fall time with 1000pf load ? 2.0a peak output source/sink current ? 1.8 to 5.0v input cmos compatible ? 4.5 to 13v total supply voltage ? smart logic threshold ? low jitter design ? two matched channels ? outputs can swing below ground ? low inductance package ? thermally-enhanced package applications ? medical ultrasound imaging ? piezoelectric transducer drivers ? non-destructive testing (ndt) ? pin diode driver ? ccd clock driver/buffer ? high speed level translator general description the supertex md1213 is a high speed, dual mosfet driver. it is designed to drive high voltage p and n-channel mosfet transistors for medical ultrasound and other applications requiring a high output current for a capacitive load. the high-speed input stage of the md1213 can operate from 1.8 to 5.0v logic interface with an optimum operating input signal range of 1.8 to 3.3v. an adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. the input logic levels may be ground referenced, even though the driver is putting out bipolar signals. the level translator uses a proprietary circuit, which provides dc coupling together with high-speed operation. the output stage of the md1213 has separate power connections enabling the output signal l and h levels to be chosen independently from the supply voltages used for the majority of the circuit. as an example, the input logic levels may be 0 and 1.8v, the control logic may be powered by +5.0 to -5.0v, and the output l and h levels may be varied anywhere over the range of -5.0 to +5.0v. the output stage is capable of peak currents of up to 2.0a, depending on the supply voltages used and load capacitance present. the oe pin serves a dual purpose. first, its logic h level is used to compute the threshold voltage level for the channel input level translators. secondly, when oe is low, the outputs are disabled, with the a output high and the b output low. this assists in properly pre-charging the ac coupling capacitors that may be used in series in the gate drive circuit of an external pmos and nmos transistor pair. typical application circuit high speed dual mosfet driver v dd 2 vh vl ina outa inb oe v ss 2 vl outb v ss 2 v dd 2 vh v ss 1 gnd v dd 1 supertex tc6320 1.0f -100v topiezoelectric tr ansducer 10nf 10nf 0.47f +5.0v md1213 3.3v cmos logic inputs 0.47f -5.0v 1.0f +100v level shifter level shifter level shifter downloaded from: http:///
2 md1213 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com ordering information device 12-lead qfn 4.00x4.00mm body 1.00mm height (max) 0.80mm pitch md1213 MD1213K6-G absolute maximum ratings parameter value v dd - v ss , logic supply voltage -0.5v to +13.5v v h , output high supply voltage v l -0.5v to v dd +0.5v v l , output low supply voltage v ss -0.5v to v h +0.5v v ss , low side supply voltage -7.0v to +0.5v logic input levels v ss -0.5v to gnd +7.0v maximum junction temperature +125c storage temperature -65c to 150c operating temperature -20c to 85c thermal resistance to air, ja 47c/w thermal resistance to case, jc 7.0c/w -g indicates package is rohs compliant (green) absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. note: 1. 1oz. 4-layer 3x4 pcb with thermal pad and thermal via array. pin coniguration 1 12 dc electrical characteristics(over operating conditions unless otherwise speciied, v h = v dd1 = v dd2 = 12v, v l = v ss1 = v ss2 = 0v, v oe = 3.3v, t a = 25c) sym parameter min typ max units conditions v dd - v ss logic supply voltage 4.5 - 13 v 2.5v v dd 13v v ss logic side supply voltage -5.5 - 0 v --- v h output high supply voltage v ss +2.0 - v dd v --- v l output low supply voltage v ss - v dd -2.0 v --- i dd1q v dd1 quiescent current - 0.55 - ma no input transitions i dd2q v dd2 quiescent current - - 10 a i hq v h quiescent current - - 10 a i dd1 v dd1 average current - 0.88 - ma one channel on at 5.0mhz,no load i dd2 v dd2 average current - 6.6 - ma i h v h average current - 23 - ma v ih input logic voltage high v oe -0.3 - 5.0 v for logic inputs ina and inb v il input logic voltage low 0 - 0.3 v i ih input logic current high - - 1.0 a i il input logic current low - - 1.0 a package marking 1213 ywll y = last digit of year sealedw = code for week sealed l = lot number = green packaging 12-lead qfn (k6) 12-lead qfn (k6) (top view) package may or may not include the following marks: si or downloaded from: http:///
3 md1213 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com logic truth table dc electrical characteristics (cont.) (over operating conditions unless otherwise speciied, v h = v dd1 = v dd2 = 12v, v l = v ss1 = v ss2 = 0v, v oe = 3.3v, t a = 25c) sym parameter min typ max units conditions v ih oe input logic voltage high 1.8 - 5.0 v for logic input oe v il oe input logic voltage low 0 - 0.3 v r in oe input logic impedance to gnd 12 20 30 k c in logic input capacitance - 5.0 10 pf all inputs outputs (v h = v dd1 = v dd2 = 12v, v l = v ss1 = v ss2 = 0v, v oe = 3.3v, t a = 25c) r sink output sink resistance - - 12.5 i sink = 50ma r source output source resistance - - 12.5 i source = 50ma i sink peak output sink current - 2.0 - a --- i source peak output source current - 2.0 - a --- ac electrical characteristics (v h = v dd1 = v dd2 = 12v, v l = v ss1 = v ss2 = 0v, v oe = 3.3v, t a = 25c) sym parameter min typ max units conditions t irf inputs or oe rise & fall time - - 10 ns logic input edge speed requirement t plh propagation delay when output is from low to high - 7.0 - ns c load = 1000pf, see timing diagraminput signal rise/fall time of 2ns t phl propagation delay when output is from high to low - 7.0 - ns t poe propagation delay oe to outputs - 9.0 - ns t r output rise time - 6.0 - ns t f output fall time - 6.0 - ns l t r - t f l rise and fall time matching - 1.0 - ns for each channel l t plh - t phl l propagation low to high and high to low matching - 1.0 - ns t dm propagation delay match - 2.0 - ns device to device delay match logic inputs output oe ina inb outa outb h l l v h v h h l h v h v l h h l v l v h h h h v l v l l x x v h v l downloaded from: http:///
4 md1213 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com propagation delay logic input threshold 1.0 1.5 2.0 2.5 3.0 3.5 10 9.08.0 7.0 6.0 propagation delay vs. logic voltage logic voltage (v) propagation delay (ns) 0 1.0 2.0 3.0 4.0 5.0 2.52.0 1.5 1.0 0.5 0 v th vs. v oe v oe (volts) v th (volts) v oe /2 0.6v detailed block diagram v dd 2 v h vl ina outa inb oe v ss 2 vl outb v ss 2 v dd 2 vh v ss 1 gnd v dd 1 sub level shifter level shifter level shifter downloaded from: http:///
5 md1213 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com in t plh 10% out t phl t r 90% 10% t f 3.3v 0v 0v 90% 50% 50% timing diagram simpliied block diagram vl vss2 vss1 gnd outaoutb vdd2 vh inainb oe vdd1 md1213 v dd 2 v h v l ina outa inb oe v ss 2 v l outb v ss 2 v dd 2 v h v ss 1 gnd v dd 1 supertex tc6320 1.0f -100v to piezoelectric tr ansducer 10nf 10nf 0.47f +5. 0 v md1213 3.3v cmos logic inputs 1.0f +100v level shifter level shifter level shifter single supply application circuit downloaded from: http:///
6 md1213 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com application information for proper operation of the md1213, low inductance bypass capacitors should be used on the various supply pins. the gnd input pin should be connected to the digital ground. the ina, inb, and oe pins should be connected to their logic source with a swing of gnd to logic level high, which is 1.8 to 5.0v. good trace practices should be followed cor - responding to the desired operating speed. the internal cir - cuitry of the md1213 is capable of operating up to 100mhz, with the primary speed limitation being the loading effects of the load capacitance. because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. unless the load speciically requires bipolar drive, the vss1, vss2, and vl pins should have low inductance feed-through connections directly to a ground plane. if these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. the power connections vdd1 and vdd2 should have a ceramic by - pass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. a common capacitor and voltage source may be used for these two pins, which should always have the same dc voltage applied. for applications sensitive to jitter and noise, separate decoupling networks may be used for vdd1 and vdd2. the supplied voltages of vh and vl determine the output logic levels. these two pins can draw fast transient currents of up to 2.0a, so they should be provided with an appropri - ate bypass capacitor located next to the chip pins. a ceramic capacitor of up to 1.0f may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. pay particular attention to minimiz - ing trace lengths and using suficient trace width to reduce inductance. surface mount components are highly recom - mended. since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistor in series with the output signal to obtain better wave - form integrity at the load terminals.this will of course reduce the output voltage slew rate at the terminals of a capacitive load. pay particular attention to the parasitic coupling from the driver output to the input signal terminals. this feedback may cause oscillations or spurious waveform shapes on the edges of signal transi - tions. since the input operates with signals down to 1.8v, even small coupled voltages may cause problems. use of a solid ground plane and good power and signal layout prac - tices will prevent this problem. be careful that the circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the in - put logic circuitry. pin description pin # name description 1 ina logic input. controls outa when oe is high. input logic high will cause the output to swing to vl. input logic low will cause the output to swing to vh. 2 vl supply voltage for n-channel output stage. 3 inb logic input. controls outb when oe is high. input logic high will cause the output to swing to vl. input logic low will cause the output to swing to vh. 4 gnd logic input ground reference. 5 vss1 low side analog circuit and level shifter supply voltage. should be at the same potential as vss2. 6 vss2 low side gate drive supply voltage. 7 outb output driver. swings from vh to vl. intended to drive the gate of an external n-channel mosfet via a series capacitor. when oe is low, the output is disabled. outb will swing to vl turning off the external n-channel mosfet. 8 vh supply voltage for p-channel output stage. 9 outa output driver. swings from vh to vl. intended to drive the gate of an external p-channel mosfet via a series capacitor. when oe is low, the output is disabled. outa will swing to vh turning off the external p-channel mosfet. 10 vdd2 high side gate drive supply voltage. 11 vdd1 high side analog circuit and level shifter supply voltage. should be at the same potential as vdd2. 12 oe output-enable logic input. when oe is high, (v oe + v gnd )/2 sets the threshold transition between logic level high and low for ina and inb. when oe is low, outa is at vh and outb is at vl regardless of ina and inb notes: 1. thermal pad and pin #5 (vss1) must be connected externally. 2. index pad and thermal pad are connected internally downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. supertex inc . does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2012 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 7 md1213 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-md1213 b011612 12-lead qfn package outline (k6) 4.00x4.00mm body, 1.00mm height (max), 0.80mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.25 3.85* 0.75 3.85* 0.75 0.80 bsc 0.35 0.00 0 o nom 0.90 0.02 0.30 4.00 1.70 4.00 1.70 0.55 - - max 1.00 0.05 0.35 4.15* 2.25 4.15* 2.25 0.75 0.15 14 o jedec registration mo-220, variation vggb, issue k, june 2006. * this dimension is not speciied in the jedec drawing. drawings not to scale. supertex doc. #: dspd-12qfnk64x4p080, version c041309. seating plane to p v iew side view bottom view a a1 d e d2 e b e2 a3 l l1 vi ew b vi ew b 1 12 note 3 note 2 note 1(index area d/2 x e/2) note 1(index area d/2 x e/2) 1 12 notes: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. downloaded from: http:///
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